1. Field of the Invention
The present invention relates to an image sensing apparatus for digitizing image information of an original target and transmitting the information to computer systems.
2. Description of the Related Art
Some computer systems like personal computers and word processors are equipped with an image scanner, which scans an original target and reads the target's image information. Recently available are computer systems that include an electronic camera that senses a dynamic image as well as a three-dimensional image. The camera sends image data to the computer via a bus line. Such electronic cameras digitize image information and transmit the digitized data to computer systems.
FIG. 3 is a block diagram showing a conventional image sensing apparatus for digitizing image information and for outputting the digitized data (image data). A solid state image sensor 1 is constituted by a CCD (charge coupled device) having a plurality of light-receiving elements aligned in a matrix form and a plurality of shift registers corresponding to each light-receiving element. The sensor 1 stores information charges at each light-receiving element, which correspond to the image pattern of a subject. A CCD driver 2 produces a multi-phase clock pulse signal based on horizontal and vertical scan timing signals each synchronous with the horizontal and vertical scan timings. The CCD driver 2 provides the CCD 1 with the multi-phase clock pulse signal. This allows the CCD 1 to be driven in accordance the timing pulse based on the horizontal and vertical scan timing signals. The information charges stored in each light-receiving element are sequentially outputted via the corresponding shift register at a predetermined timing. Each information charge packet is converted to a voltage value in an output interface of the CCD 1. Then, sets of image signals, each of which corresponds to a line of light-receiving elements, are continuously outputted line by line.
A timing controller 3 includes a counter and a decoder. The timing controller 3 inputs a reference clock having a given period and produces timing signals of horizontal and vertical scanning period. When pursuant to the NTSC (National Television System Committee) standard, the timing controller 3 inputs a reference clock signal of 14.32 MHz. The timing controller then produces a horizontal timing signal by frequency-dividing the reference clock signal into 1/910 and produces a vertical timing signal by frequency-dividing the produced horizontal timing signal into 2/525.
A signal processor 4 shapes image signals from the CCD 1 into a predetermined format by performing a sample and hold operation, AGC (automatic gain control), etc. to the signals. For example, in the sample and hold operation, a reference level and a signal level are alternately outputted with a predetermined interval in between. Data corresponding to the difference between the reference level and the signal level is acquired as a sample. On the other hand, in the AGC operation, the gain to the image signal is adjusted so that the average level of the image signals on a screen is contained in a proper range.
An A/D converter 5 operates in synchronism with the drive timing of the CCD 1 and quantizes the image signals from the signal processor 4 pixel by pixel for producing digitized image data corresponding to each light-receiving element on the CCD 1. The image data is sent to a bus line from an output buffer and then transmitted to a computer system via the bus line. The above described circuits, which constitute an image sensing apparatus, are formed as integrated circuits and provided on a circuit board. The circuits are connected one another by wiring.
It has been proposed to manufacture a 3-chip image sensing apparatus which has a chip including an output buffer, the timing controller 3, the signal processor 4 and the A/D converter, a one-chip CCD 1 and a one-chip driver 2. In general, the digital-operating timing controller 3 and the digital-operating A/D converter 5 consist of MOS transistors, while the chiefly analog-operating signal processor 4 consists of bipolar transistors. This means that MOS transistors and bipolar transistors have to be formed on a single substrate to manufacture a one-chip device having the output buffer, the timing controller 3, the signal processor 4 and the A/D converter 5 thereon.
However, forming MOS transistors and bipolar transistors on a single substrate requires such a complicated procedure that normally all the circuits on the board are formed with MOS transistors. That is, the signal processor 4 is constituted by MOS transistors that are made to analog-operate. The signal processor 4 is integrated on a single semiconductor substrate with the timing controller 3, the A/D converter 5 and the output buffer, which are constituted by digital-operating MOS transistors.
An analog-operating MOS transistor has a better characteristic when it is constituted by an N channel-type transistor, in which electrons have great mobility in the channel area. In this case, the N-channel type MOS transistor needs to be formed in an electrically isolated P type diffusion area (P-well area). A substrate of N-type conductivity is generally utilized for this purpose. This allows the source of the MOS transistor to be short-circuited to the substrate for preventing back gate bias effect.
The signal processor 4, which receives signals from the CCD 1, is generally driven by a supply voltage of 5 V for a wider input dynamic range, while the bus line for transmitting image data is preferably driven by a supply voltage of 3.3 V for reducing the consumed power. One method for driving the bus line by a supply voltage of 3.3 V is to mount the signal processor 4 and the A/D converter 5 on a single chip and to output image data having a peak value of 5 V. This requires a level converter between the output buffer and the bus line.
Mounting the signal processor 4, the A/D converter 5 and the output buffer on a single chip eliminates the necessity of the level converter. It also enables outputting of image data with a peak value of 3.3 V by driving the chip with two separate supply voltages, for example, by driving the signal processor with a supply voltage of 5 V and driving the output buffer with a supply voltage of 3.3 V. Semiconductor substrates of N type conductivity are suitable for forming analog-operating MOS transistors. However, since supply voltage is applied to the substrate, a semiconductor substrate of N-type conductivity cannot have a plurality of different supply voltages. Thus, an integrated circuit device including the signal processor 4, timing controller 3 and the output buffer, which are mounted on a single chip, cannot be driven by two different supply voltages.